1. Field of the Invention
The present invention relates to a multi-processing system that distributes workload optimally among a plurality of processor chips without stopping the operation thereof.
2. Description of the Related Art
Conventionally, when processing of a large amount of information that can not be processed by the function of one (1) processor chip is executed, a multi-processing system that distributes the processing to a plurality of processors and causes the processors to execute the processing is utilized. In the multi-processing system, the distribution of the processing to be executed by the processor chips respectively is determined corresponding to clock frequency that indicates the processing performance of each processor chip.
FIG. 1 is a block diagram of the hardware configuration of a conventional multi-processing system. In FIG. 1, a conventional multi-processing system 900 is configured by connecting a distributed processing control chip 920 to a plurality of processor chips 910. Because the number of the processor chips is two (2) in FIG. 1, the chips are denoted respectively by “processor chip 910A” and “processor chip 910B”.
Each of the processor chip 910A and the processor chip 910B includes a processor circuit 911 consisting of a clock unit 911a and a core unit 911b. The processor circuit generates a clock signal using the clock unit 911a. The generated clock signal is inputted into the core unit 911b. The core unit 911b executes processing distributed by a distributed processing control circuit 921 of the distributed processing control chip 920 based on the inputted clock signal.
Each of the processor chips 910 consists of a semiconductor circuit. Though the processor chips 910 are of the same type, the semiconductor circuit constituting each of the processor chips 910 may be a quick-operating circuit or a slow-operating circuit due to the performance unevenness caused during the manufacture thereof. For the semiconductor circuit constituting each of the processor chips 910, the operating speed thereof is varied according to the temperature. Therefore, the slowest-operating clock frequency in the frequencies estimated respectively for the chips is defined in the specifications such that the lot-to-lot variation and the range of the temperature variation are met.
In general, the specifications for the processor chips 910 is defined such that the specifications are unified specifications according to the type of the processor chips 910. Therefore, every processor chip 910 of the same type is regarded to follow uniquely the same specifications.
It is assumed that, for both of the processor chip 910A and the processor chip 910B, the specifications thereof define that the chips 910A, 910B are operable at the maximum clock frequency of 1 GHz. In this case, after the multi-processing system 900 has been energized, the clock frequency, the power source voltage, and the substrate potential are determined such that those items meet the specifications. That is, in the multi-processing system 900 shown in FIG. 1, the clock frequency of both of the processor chip 910A and the processor chip 910B is set at 1 GHz. Thereafter, processing is started in each of the processor chips 910.
In addition to the multi-processing system that utilizes as it is the clock frequency defined as the specifications thereof as described above, a technique that distributes a clock frequency autonomously according to processing has been developed. As an example, a circuit is disclosed (see, for example, Japanese Patent Application Laid-Open Publication No. 2004-228417), that includes a plurality of functional modules and a performance measuring circuit provided on a processor chip, and a memory table circuit (MTC) that stores information on the processor chip.
By configuring the circuit as described above, the operation of the processor chip is autonomously set by calculating the clock frequency, the power source voltage, and the substrate potential in a autonomous and distributed manner, from the performance of the processor chip measured by PMC and the values stored in PMC. Therefore, even in the case for functional modules for which the operation performance during operation is specified, the optimal clock frequency can be set according to the lot-to-lot variation of the processor chips.
However, even when the processor chips 910 are of the same type, the clock frequency of each of the chips 910 is varied due to the lot-to-lot variation and the temperature of each semiconductor circuit constituting each of the processor chips 910. Therefore, a problem has arisen that the processing performance of each of the processor chips 910A, 910B can not be utilized to the maximum thereof when the same type of the processor chips 910 are operated as following the same specifications uniquely.
For example, it is assumed that, though the processor chip 910A and the processor chip 910B are of the same type and the temperature of each semiconductor circuit is same, the processor chip 910A can operate at 2 GHz and the processor chip 910B can only operate up to 1 GHz due to the lot-to-lot variation.
In this case, both of the processor chip 910A and the processor chip 910B would conventionally be operated at 1 GHz according to the specifications. Representing the processing performance per 1 GHz of one (1) processor chip as “Pv”, the performance of the multi-processing system 900 can be expressed in the following Equation (1).(1 GHz+1 GHz)×Pv=2Pv  (1)
However, the processor chip 910A has the actual capacity to operate at up to 2 GHz. Therefore, the processing performance of the multi-processing system 900 obtained when the chips are operated at the clock frequency according to the actual capacity thereof, can be expressed in the following Equation (2).(2 GHz+1 GHz)×Pv=3Pv  (2)
Comparing the above Equation (1) to Equation (2), only two thirds (⅔) of the processing performance within the actual capacity can be utilized in the conventional technique.
In the conventional multi-processing system, the ratio between the required processing amounts that the chip can most quickly process can not be specified because the processing performance of the processor chips 910 can not be recognized. Therefore, the required processing amounts respectively for the processor chips 910A, 910B have to be distributed in the ratio of 1:1 at the clock frequency defined in the specification. Therefore, a problem has arisen that processing distribution corresponding to the processing performance of each of the processor chips 910A, 910B can not be realized.
When the processor chips 910 are replaced, the distribution has to be executed according to clock frequencies defined in the specifications because the processing performance of each of the newly mounted processor chips can not be recognized.
The conventional technique in Japanese Patent Application Laid-Open Publication No. 2004-228417 described above has a problem that the processing for the entire system can not be distributed optimally because the function is of autonomous-distributing type.